1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device having memory cells.
2. Description of the Prior Art
In the memory cell region of the FeRAM (Ferroelectric Random Access Memory), a plurality of ferroelectric capacitors are formed on the insulating film vertically and horizontally. The ferroelectric capacitors of the FeRAM that are mass-produced currently have a planar structure in which contact portions are provided on upper surfaces of the lower electrodes.
FIG. 1 is a plan view showing the planar structure of the memory cell region in which the capacitors having the planar structure, the word lines, the bit lines, etc. are arranged, and connections between the memory cell region and the circuits. In this case, in FIG. 1, the insulating films are omitted from the illustration.
In FIG. 1, a plurality of active regions 101 that are surrounded by the element isolation insulating film (not shown) are formed on the surface of the semiconductor substrate. The stripe-like plate lines 102 constituting the lower electrodes of the capacitors are formed on the first interlayer insulating film (not shown) that covers the active regions 101 and the element isolation insulating film. Also, a plurality of upper electrodes 104 are formed at an interval over the plate lines 102 in the length direction. In addition, the ferroelectric films 103 are formed between the plate lines 102 and the upper electrodes 104.
In this structure, the ferroelectric capacitor is constructed by the upper electrode 104, the ferroelectric film 103, and the plate line (lower electrode) 102. That is, the ferroelectric capacitors are formed on one plate line 102 as many as the upper electrodes 104.
The active region 101 is formed in plural at an interval under the region between the neighboring plate lines 102 in the plate-line extending direction. Two word lines 105 that extend in the length direction of the plate line 102 are formed at an interval on the active regions 101 between the plate lines 102. The word lines 105 are formed on the active regions 101 via the gate insulating film to extend onto the element isolation insulating film. The word line 105 functions as the gate electrode of the MOS transistor on the active region 101. Also, the impurity diffusion regions serving as the source/drain of the MOS transistor are formed in the active region 101 on both sides of the word line 105.
Accordingly, two MOS transistors that use one impurity diffusion region commonly are formed in respective active regions 101 that are present between two plate lines 102. The MOS transistors and the word lines 105 are covered with the first interlayer insulating film, and the ferroelectric capacitors are covered with the second insulating film (not shown).
The first contact holes 106 are formed in the first and second interlayer insulating films on the active region 101 on both sides of the word lines 105, and the second contact holes 107 are formed in the second insulating film on the upper electrodes 104. The conductive plugs are buried in the first and second contact holes 106, 107.
The impurity diffusion region in the active region 101 between the upper electrode 104 and the word line 105 is connected electrically to the upper electrode 104 via the metal wiring 108 on the second interlayer insulating film and the conductive plugs in the first and second contact holes 106, 107. Also, the impurity diffusion region in the active region 101 put between two word lines 105 is connected electrically to the metal pad 109 on the second interlayer insulating film via the conductive plug in the first contact holes 106.
The third interlayer insulating film (not shown) is formed on the metal wiring 108 and the metal pad 109. The bit line 110 formed on the third interlayer insulating film is connected electrically to the impurity diffusion region at the center of the active region 101 via the metal pad 109. The bit line 110 is formed in plural at an interval to extend in the direction that intersects orthogonally with the plate line 102.
A plurality of bit lines 110 are connected to the sense amplifier SA in the memory cell region respectively except the first and final bit lines. Also, a plurality of plate lines 102 are connected to the plate line driver PD in the memory cell region respectively except the first and final plate lines. In addition, the word lines 105 are connected to the word line driver WD in the memory cell region respectively except the first and final word lines.
In the memory cell region, two outermost plate lines 102 and two outermost bit lines 110 are connected to the fixed potential, e.g., the ground voltage, respectively.
Accordingly, the outermost peripheral region in the memory cell region is the dummy capacitor region 120, and the ferroelectric capacitors being positioned in the dummy capacitor region 120 are used as the dummy capacitors that are not actually operated. Also, the ferroelectric capacitors being surrounded by the dummy capacitor region 120 become the memory cells.
In this case, it is set forth in following Patent Document 1 that the dummy capacitors are formed uniformly along the outermost periphery of the memory cell region of the DRAM.
Also, it is set forth in following Patent Document 2 that, if the long side of the upper electrode of the ferroelectric capacitor is arranged perpendicularly to the long side of the lower electrode and also the contact hole that is formed on the upper electrode is displaced along the long side direction, variation in capacitor characteristic is reduced.
However, in order to improve characteristics of the capacitor that is actually operated in the initial state, the formation of the dummy capacitor is needed in the prior art.
(Patent Document 1)
Patent Application Publication (KOKAI) Hei 11-345946 (on and after page 14, line 19 in Specification, FIG. 3)
(Patent Document 2)
International Publication 97/40531 Pamphlet (Specification page 14, line 19 et seq., FIG. 1 to FIG. 3)
In the meanwhile, the optimum arrangement and structure of the dummy capacitors are not clear, and thus the state of the deterioration of the capacitor is different according to the arrangement and structure of the memory cell.
Also, the deterioration of the capacitor appears conspicuously as the memory cell area is reduced in response to the request for the higher integration of the FeRAM. But the rule to reduce the arrangement of the dummy capacitors to the lowest minimum is not apparent.